tugas VHDL

program multiplexter dengan menggunakan operator

dibawah ini list programnya

library ieee ;
use ieee.std_logic_1164.all;

entity mux_1 is

port

(a,b,c,d : in std_logic;

sel: in std_logic (1 downto 0);

y: out std_logic;

end mux_1;

architecture arc_mux of mux_1 is

begin

with sel select

y<= a when "00";

b when "01";

c when "10";

d when others;

end arc_mux;

selamat mencoba......!

buatlah decoder 3 to 8 dengan menggunakan operator.

dibawah ini list programnya..

library ieee ;
use ieee.std_logic_1164.all;
entity 3to8decoder is
port (
a, b, c : in std_logic ;
y : out std_logic_vector (7 downto 0) ) ;
end decoder ;

architecture arcdecoder of 3to8decoder is
signal abc : std_logic_vector (2 downto 0) ;
begin
abc <= a & b & c ;
with abc select y <=
"00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others ;
end arcdecoder ;

selamat mencoba...